> Even if it is possible, what machanism will maintain coherency between the
> cache and the remote memory which is seen through the system that has been
> described in the initial mail.
Of course, I understand coherency issue.
Since this system is early experimental, we force strong limitation to
application programmer (i.e. before reading buffer mapped to remote node's
memory, application explicitly must invalidate cache associated.)
Finally, we will implement coherency mechanism on NIC (hopefully...).
Also, I understand PCI mastar capable device is the appropriate solution
for these performance issue, but I'd like to try squeeze out performance
from current H/W implementation as possible as I can.
Before Linux implementation, my colleague wrote very basic device
driver on Windows/NT. On WIndows/NT, he can map such PCI address space
(finally mapped to remote node's memory) as Cachable,
and observed 'Read Multiple' (or 'Read Line' not sure, sorry) transaction
on PCI bus (monitored with PCI analyzer).
So, I'd like to implement same feature (access method) on Linux (if possible).
Thank you again!
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