Re: Cache flushing...

Andrew Cagney (
Sun, 2 Jul 1995 15:03:39 +1000 (EST)

Excerpts from mail: 1-Jul-95 Cache flushing... "David S. Miller"@caip.r (11192)

> 3) Virtually indexed caches, tagged by physical address

> These caches have their lines indexed by virtual address,
> however the tag bits are from the physical address after the virtual
> address is translated in the MMU.

> e) Shared memory - Shared regions between processes must
> either be mapped at the same exact virtual addresses or
> addresses that are exactly some number of the cache size
apart from each other.


I believe that for all the current 32bit PowerPC implementations, the
architecture has been very carefully designed so that:

o cache lines (blocks) are 2^5 bytes
o there are 2^7 sets
o there are 2(603), 4(604,603+?), 8(601) blocks per set

In addition the cache is:

o virtually indexed (from the above, PPC bits 20-26)
o physically taged

Working this through you find that a block (for all sets) covers exactly
one 4k page ( == PPC page size) and as a consequence, this means that
for the PowerPC, the above is a none issue (and very nice change at that

As for a POWER machine ...


(Hope I got the numbers correct :-)