Re: Cache flushing...

Tim Olson (
Sun, 2 Jul 1995 08:35:27 -0500 (CDT)

| FYI,
| I believe that for all the current 32bit PowerPC implementations, the
| architecture has been very carefully designed so that:
| o cache lines (blocks) are 2^5 bytes
| o there are 2^7 sets
| o there are 2(603), 4(604,603+?), 8(601) blocks per set

On the 601, lines and blocks are not equivalent: the 601 has 64-byte
lines, split into two sectors (blocks). The two sectors share the
tag, but have separate status bits. This means that all of the cache
block operations work on 32-byte blocks, just as on 603 & 604.
However, the 601 has half as many sets as the others because of its
64-byte line.

| In addition the cache is:
| o virtually indexed (from the above, PPC bits 20-26)
| o physically taged

The bits used to index into the tag array are 21:26 for 601, 20:26 for
603, 604. All of these bits are in the page index range of the
address, meaning that they are unmodified by address translation.
Hence the processors are physically indexed.

Tim Olson
Apple Computer / Somerset