On Mon, 14 Feb 2000, Alan Cox wrote:
> > > IRQ7 is also raised to indicate a spurious interrupt (ie nobody owning up
> > > to having requested it). That is one reason its used for the parallel port
> > > on a PC - the odd extra irq does no harm
> > >
> >
> > This is not possible. Hardware interrupts are created by hardware.
>
> Then the IBM PC violates the laws of causality and physics. I would suggest
> you read the chipset documentation however.
>
> The 8259 generates IRQ7 (or IRQ 15) when an interrupt device deasserts its
> line before the PIC receives an INTA pulse from the CPU.
> [ or in actual fact during some of the other phases that go with this ]
>
> Its in the manual. It says so. It happens.
>
If a hardware device asserts its interrupt line long enough for the
interrupt controller to see it, it is latched. That is how the interrupt
controller 'remembers' that an interrupt occurred. It doesn't care
if the interrupt line is deasserted before the CPU is notified. In fact,
because of the priority of higher-priority pending interrupts the
CPU probably won't know about it right away. That's why any pending
hardware interrupts are latched.
I do know about this chipset.
Cheers,
Dick Johnson
Penguin : Linux version 2.3.41 on an i686 machine (800.63 BogoMips).
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