--650352740-1085431359-943526905=:2579
Content-Type: TEXT/PLAIN; CHARSET=US-ASCII
Content-ID: <Pine.LNX.4.10.9911251148311.2579@chiara.csoma.elte.hu>
the attached patch completes the memory-ordering changes started by the
spin_unlock() change in 2.3.30-pre1. Here is the gist of the patch:
/*
* Force strict CPU ordering.
* And yes, this is required on UP too when we're talking
* to devices. Note that these primitives deal with operation
* ordering, not atomicity.
*
* For now, "wmb()" doesn't actually do anything, as all
* Intel CPU's follow what Intel calls a *Processor Order*,
* in which all writes are seen in the program order even
* outside the CPU.
*
* rmb(): writes are guaranteed by Intel to never pass reads
* (in an externally visible way that is), so the read barrier
* is just a dummy store. Note that (%%esp) is ours and only
* ours, so this is IRQ-safe as well. The barrier _must_
* include a store, thus the assembly. The CPU snoops external
* devices (including CPUs and DMA agents), so this works out
* just fine in all cases and is lightweight. And this is only
* 4 bytes icache footprint total. 'addl $0, (%%esp)' is a legal
* write operation which dirties the target cacheline.
*
* We expect future Intel CPU's to have a weaker ordering. But
* it's not all that bad right now already.
*/
#define mb() __asm__ __volatile__ ("addl $0, (%%esp)": : :"memory")
#define rmb() mb()
#define wmb() __asm__ __volatile__ ("": : :"memory")
#define set_rmb(var, value) do { var = value; rmb(); } while (0)
#define set_mb(var, value) set_rmb(var, value)
#define set_wmb(var, value) do { var = value; wmb(); } while (0)
The patch works just fine on my 8-way.
-- mingo
--650352740-1085431359-943526905=:2579
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--650352740-1085431359-943526905=:2579--
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