Hello all,
I'm just acting as a liaison here. This is what the sys admins want to know
about IDE DMA "things", so I'm just forwarding on their questions.
>From Ray Pasetes (rayp@fnal.gov):
1) What are all causes for an ide bus to reset? I can see some in the
source code, but some of that stuff I don't understand. Other than
power management, are there any other causes -- i.e. what if the
cpu is at 99.9% busy and there is a request from a new process to write/read
from the disk. Will the process be temporarily blocked while until
it gets cpu to access I/O which could cause a timeout via the ide
driver and have the bus reset?
2) Would it be possible to get a debug version of the code so that we
can find out where/what/when the ide bus gets reset.
Here's more information on the systems:
Our systems are running 99.9% constant. Once an hour we force 2
1GB disk writes and 2 1GB disk reads, in addition to the current
load. The systems are configured as:
50 Eternal Graphics
Intel Lancewood (GX chipset) MB
2x PIII 500MHz CPUs
512MB memory
2x 18GB WD IDE disk drives WDC AC418000D
100 Hi-Tech PCs
ASUS P2BD MB
2x PIII 500Mhz CPUs
512MB memory
2x 17.2 GB Maxtor disk drives Maxtor 91700U5
Both systems are using Ultra 66 disk drives (could this be a problem)?
Don Holmgren also has Ultra 66 drives but has not seen this problem.
In fact, a lot of people haven't seen this problem.
Again, thanks in advance.
Dan
___________________________________________________________________________
Dan Yocum | Phone: (630) 840-8525
Linux Research and Development | Fax: (630) 840-6345
Computing Division, OSS Dept. | email: yocum@fnal.gov .~. L
Fermi National Accelerator Lab | WWW: www-oss.fnal.gov/~yocum/ /V I
P.O. Box 500 | // \ N
Batavia, IL 60510 | "TANSTAAFL" /( ) U
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