[ This is just a general comment and has nothing to do with the
persons involved in this thread. ]
dyslexia n. an abnormal difficulty in reading and spelling, caused by
a condition of the brain.
People I know are being harassed on the net for misspellings that are
caused by their dyslexia. In a public fora you don't know the other
person and something that you find funny might be perceived
differently by other people.
>
> > Xeon are that the Xeon has twice the amount of l1 and upto 2megs of l2,
> > it's l1 is also 4way set assoiative not 2, and finally it has mmx. There
>
> Are you sure the PPro is not also 4way? I was told that was the reason it
> was able to do quad setups nicely while the PII and Pentium were not.
>
This is off-topic, but you're confusing two issues. The associativity
of the L2 cache indicates how many cache-lines the cache can check in
parallel when looking up data. At the same time it indicates how well
the cache behaves wrt cache-collisions. Increasing the associativity
of the cache will generally make it more costly (more transistors).
In a CPU, the L1 cache normally has the highest associativity, the L2
has a lower associativity, and the L3 has the lowest. The reason is
that an L3 cache will be much larger than the other caches so there
will be less collisions, and since it is very large, you save more $$
by making the design cheaper. This doesn't apply to the extremely
fast L1 cache.
The "4way" you have heard of is how many processors PPro supports in
an SMP configuration. You can build 4-way PPro SMP systems without
extra hardware, but only 2-way PII SMP systems. The two "4ways" are
completely unrelated.
astor
-- Alexander Kjeldaas, Guardian Networks AS, Trondheim, Norway http://www.guardian.no/- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.rutgers.edu Please read the FAQ at http://www.tux.org/lkml/faq.html