Re: About ioremap() and L2-Cache

Alan Cox (alan@lxorguk.ukuu.org.uk)
Tue, 22 Jul 1997 21:54:44 +0100 (BST)


> I read the ioremap source of Linux-2.1.x and find the kernel doesn't
>care about the Pentium new bit setting PWT ( page cache write through ) and
> PCD ( page cache disable ), only PCD is defined but never used in the kernel

Yes. On the PC the PCD isnt an issue. PWT is on the list to add for some
drivers. However PWT turns out to be very dangerous. Enabling it for some
video cards crashes the machine for example.

> In Linux2.1.x, I can not find the bit set, if the L1-Cache or L2-Cache cache
> the I/O address space memory, how the device driver communicates with the
>device.

The PCI bios and the PC chipset are supposed to correctly set up the MSR's
for caching ranges, and the PCI chipset handles the issues of cache/nocache
for you. In effect on a PC you are allowed to let the hardware handle it.

This doesnt always quite work however, which is one reason for it being worth
being able to overrride it. I think Ingo was had code for ioremap_nocache()