damn, registers are plain memory as well, just different
indexing. Think of them as 'level 0 cache'. followed by level 1 2 3
caches and physical memory and swap and ...
But note how the parallelism bubbles out to be large at the external
parts of the hierarchy. ie. register ports are usually at least dual
ported, and L2/L3 caches are usual multiple transaction per cycle (so
DMA and cache coherency transactions and cpu accesses can occur in
parallel) but usually L1 I/D caches are single transaction per cycle.
I don't know if things are always like this on other Risc's or the
Intel, but Sparc's are mostly designed in this manner.
---------------------------------------------////
Yow! 11.26 MB/s remote host TCP bandwidth & ////
199 usec remote TCP latency over 100Mb/s ////
ethernet. Beat that! ////
-----------------------------------------////__________ o
David S. Miller, davem@caip.rutgers.edu /_____________/ / // /_/ ><