Re: Linux & ECC memory

Ray Van Tassle-CRV004 (
Fri, 15 Nov 1996 8:39:49 -0600

>From the 430HX (TXC) chipset document:
ECC Checking and Correction. When enabled, the TXC detects all single and
dual-bit errors, and corrects all single-bit errors during DRAM reads. The
corrected data is transferred to the requester (CPU or PCI). Note that the
corrected data is not written back to DRAM.

Error Reporting. When ECC is enabled and ERRCMD is used to set SERR#
functionality, ECC errors are signaled to the system via the SERR# pin. The
TXC can be programmed to signal SERR# on uncorrectable errors, correctable
errors, or both. The type of error condition is latched until cleared by
software (regardless of SERR# signaling).
When a single or multi-bit error is detected, the offending DRAM row ID is
latched in the ERRSTS register in the TXC. The latched value is held until
software explicitly clears the error status flag.

-30- Ray
> ________________________________________________________
> To:
> Cc:;
> From: on Thu, Nov 14, 1996 7:47 PM
> Subject: z-Re: Linux & ECC memory
> A more subtle issue is whether the ECC memory controller could report
> instances where ECC detection and successful correction took place. It
> would seem to be useful to provide a way for the OS to recognize that
> non-fatal memory errors have occured, even though they were repaired.