Re: [PATCH v3 4/6] media: qcom: camss: Add sc8280xp resource details

[Bryan O'Donoghue]

On 07/11/2023 21:48, Konrad Dybcio wrote:
> On 11/5/23 18:45, Bryan O'Donoghue wrote:
> > This commit describes the hardware layout for the sc8280xp for the
> > following hardware blocks:
> >
> > - 4 x VFE, 4 RDI per VFE
> > - 4 x VFE Lite, 4 RDI per VFE
> > - 4 x CSID
> > - 4 x CSID Lite
> > - 4 x CSI PHY
> >
> > Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@xxxxxxxxxx>
> > ---
> >   drivers/media/platform/qcom/camss/camss.c | 383 
> > ++++++++++++++++++++++++++++++
> >   1 file changed, 383 insertions(+)
> >
> > diff --git a/drivers/media/platform/qcom/camss/camss.c 
> > b/drivers/media/platform/qcom/camss/camss.c
> > index 8778fdc1ee342..51619842f3925 100644
> > --- a/drivers/media/platform/qcom/camss/camss.c
> > +++ b/drivers/media/platform/qcom/camss/camss.c
> > @@ -941,6 +941,374 @@ static const struct resources_icc 
> > icc_res_sm8250[] = {
> >       },
> >   };
> > +static const struct camss_subdev_resources csiphy_res_sc8280xp[] = {
> > +    /* CSIPHY0 */
> > +    {
> > +        .regulators = {},
> > +        .clock = { "csiphy0", "csiphy0_timer" },
> > +        .clock_rate = { { 400000000 },
> > +                { 300000000 } },
> > +        .reg = { "csiphy0" },
> > +        .interrupt = { "csiphy0" },
> > +        .ops = &csiphy_ops_3ph_1_0
> > +    },
> > +    /* CSIPHY1 */
> > +    {
> > +        .regulators = {},
> > +        .clock = { "csiphy1", "csiphy1_timer" },
> > +        .clock_rate = { { 400000000 },
> > +                { 300000000 } },
> > +        .reg = { "csiphy1" },
> > +        .interrupt = { "csiphy1" },
> > +        .ops = &csiphy_ops_3ph_1_0
> > +    },
> > +    /* CSIPHY2 */
> > +    {
> > +        .regulators = {},
> > +        .clock = { "csiphy2", "csiphy2_timer" },
> > +        .clock_rate = { { 400000000 },
> > +                { 300000000 } },
> > +        .reg = { "csiphy2" },
> > +        .interrupt = { "csiphy2" },
> > +        .ops = &csiphy_ops_3ph_1_0
> > +    },
> > +    /* CSIPHY3 */
> > +    {
> > +        .regulators = {},
> > +        .clock = { "csiphy3", "csiphy3_timer" },
> > +        .clock_rate = { { 400000000 },
> > +                { 300000000 } },
> > +        .reg = { "csiphy3" },
> > +        .interrupt = { "csiphy3" },
> > +        .ops = &csiphy_ops_3ph_1_0
> > +    },
> > +};
> > +
> > +static const struct camss_subdev_resources csid_res_sc8280xp[] = {
> > +    /* CSID0 */
> > +    {
> > +        .regulators = { "vdda-phy", "vdda-pll" },
> > +        .clock = { "vfe0_csid_src", "vfe0_csid", "cphy_rx_src",
> > +               "vfe0_cphy_rx", "vfe0_src", "vfe0", "vfe0_axi" },
> This looks like downstream hack copypasta.. All the _src clocks
> should be axed from here, from the camss bindings and simply be
> enabled with CLK_OPS_PARENT_ENABLE on their children (which should
> be the default for all branch clocks anyway eh)

This is a legitimate comment though, at least in principle,.

I ought to be able to drop vfe0_src and vfe0_csid_src since they should 
be the roots for vfe0 and vfe0_csid.

I will see what can be rationalised in this list tomorrow.

---
bod