Re: [PATCH v4 04/42] clk: ep93xx: add DT support for Cirrus EP93xx

[Stephen Boyd]

Quoting Nikita Shubin via B4 Relay (2023-09-15 01:10:46)
> diff --git a/drivers/clk/clk-ep93xx.c b/drivers/clk/clk-ep93xx.c
> new file mode 100644
> index 000000000000..e8d3bd595255
> --- /dev/null
> +++ b/drivers/clk/clk-ep93xx.c
> @@ -0,0 +1,753 @@
> +// SPDX-License-Identifier: GPL-2.0-or-later
> +/*
> + * Clock control for Cirrus EP93xx chips.
[...]
> +#define EP93XX_SYSCON_KEYTCHCLKDIV_KEN 15
> +#define EP93XX_SYSCON_KEYTCHCLKDIV_KDIV        0
> +#define EP93XX_SYSCON_CHIPID           0x94
> +#define EP93XX_SYSCON_CHIPID_ID                0x9213
> +
> +static const char adc_divisors[] = { 16, 4 };
> +static const char sclk_divisors[] = { 2, 4 };
> +static const char lrclk_divisors[] = { 32, 64, 128 };
> +
> +static const struct clk_parent_data ep93xx_clk_parents[] = {
> +       { .fw_name = "xtali", .name = "xtali" },

Drop name. And please drop fw_name too and set .index to 0 explicitly.

> +       { .index = -1, .name = "pll1" },
> +       { .index = -1, .name = "pll2" },

These two should come from DT via index as well. The binding should be
changed to list the pll. In the previous review you mentioned the SoC
driver was populating these. The answer is yes that you should be
providing an OF clk provider (and updating the binding) to provide those
clks to this device node. Otherwise it won't be possible to describe the
connection besides with the name fallback method, which is not desired.

> +};
> +