Re: [PATCH V3 4/4] arm64: dts: qcom: ipq5018: Add tsens node

From: Sricharan Ramabadhran
Date: Sun Sep 24 2023 - 22:09:43 EST




On 9/24/2023 12:18 AM, Dmitry Baryshkov wrote:
On Fri, 22 Sept 2023 at 14:51, Sricharan R
<srichara@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx> wrote:

From: Sricharan Ramabadhran <quic_srichara@xxxxxxxxxxx>

IPQ5018 has tsens V1.0 IP with 4 sensors.
There is no RPM, so tsens has to be manually enabled. Adding the tsens
and nvmem node and IPQ5018 has 4 thermal sensors (zones). With the
critical temperature being 120'C and action is to reboot. Adding all
the 4 zones here.

Signed-off-by: Sricharan Ramabadhran <quic_srichara@xxxxxxxxxxx>
---
[v3] Ordered the qfprom device node properties as per
Krzysztof's comments

arch/arm64/boot/dts/qcom/ipq5018.dtsi | 169 ++++++++++++++++++++++++++
1 file changed, 169 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
index 9f13d2dcdfd5..9e28b54ebcbd 100644
--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
@@ -93,6 +93,117 @@ soc: soc@0 {
#size-cells = <1>;
ranges = <0 0 0 0xffffffff>;

+ qfprom: qfprom@a0000 {
+ compatible = "qcom,ipq5018-qfprom", "qcom,qfprom";
+ reg = <0xa0000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ tsens_base1: base1@249 {
+ reg = <0x249 2>;
+ bits = <3 8>;
+ };
+
+ tsens_base2: base2@24a {
+ reg = <0x24a 2>;
+ bits = <3 8>;
+ };

Sort by the address, please, as usual.


ok.

<..>


+ thermal-zones {
+ ubi32-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens 1>;
+
+ trips {
+ ubi32-critical {
+ temperature = <120000>;
+ hysteresis = <2>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-thermal {

'c' < 'u'. Please sort the nodes here.

ok

Regards,
Sricharan