Re: [PATCH 3/3] net: phy: at803x: add qca8081 fifo reset on the link down

[Jie Luo]

On 7/1/2023 10:34 PM, Andrew Lunn wrote:
> > Hi Andrew,
> > This block includes MII and MMD1 registers, which mainly configure the PLL
> > clocks, reset and calibration of the interface sgmii, there is no related
> > Clause 73 control register in this block.
>
> O.K. What does it have in the MII ID registers? Does Linux think it is
> a PHY and instantiating an generic PHY driver for it?
>
> 	Andrew
Hi Andrew,
it is the PLL related registers, there is no PHY ID existed in MII 
register 2, 3 of this block, so it can't be instantiated as the generic 
PHY device.