Re: [PATCH 3/3] net: phy: at803x: add qca8081 fifo reset on the link down
From: Andrew Lunn
Date: Sat Jul 01 2023 - 10:34:27 EST
> Hi Andrew,
> This block includes MII and MMD1 registers, which mainly configure the PLL
> clocks, reset and calibration of the interface sgmii, there is no related
> Clause 73 control register in this block.
O.K. What does it have in the MII ID registers? Does Linux think it is
a PHY and instantiating an generic PHY driver for it?
Andrew