Re: [EXT] Re: [PATCH v5 2/2] misc: nxp-sr1xx: UWB driver support for sr1xx series chip

From: Manjunatha Venkatesh
Date: Tue Dec 20 2022 - 09:34:01 EST



On 11/30/2022 12:53 PM, Greg Kroah-Hartman wrote:
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On Wed, Nov 30, 2022 at 09:39:59AM +0530, Manjunatha Venkatesh wrote:
On 10/7/2022 8:27 PM, Greg Kroah-Hartman wrote:
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On Fri, Oct 07, 2022 at 07:34:25PM +0530, Manjunatha Venkatesh wrote:
On 9/14/2022 8:39 PM, Arnd Bergmann wrote:
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On Wed, Sep 14, 2022, at 4:29 PM, Manjunatha Venkatesh wrote:

NXP has SR1XX family of UWB Subsystems (UWBS) devices. SR1XX SOCs
are FiRa Compliant. SR1XX SOCs are flash less devices and they need
Firmware Download on every device boot. More details on the SR1XX Family
can be found athttps://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fwww.nxp.com%2Fproducts%2F%3AUWB-TRIMENSION&data=05%7C01%7Cmanjunatha.venkatesh%40nxp.com%7C46c5718c03ee429cf57208dad2a3cad7%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C638053898170779252%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&sdata=S2BswHaF22edAfiZXEKUwGfUTNi1nuQzQSdGDb26peI%3D&reserved=0

The sr1xx driver work the SR1XX Family of UWBS, and uses UWB Controller
Interface (UCI). The corresponding details are available in the FiRa
Consortium Website (https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fwww.firaconsortium.org%2F&data=05%7C01%7Cmanjunatha.venkatesh%40nxp.com%7C46c5718c03ee429cf57208dad2a3cad7%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C638053898170779252%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&sdata=0fFcimUd6gOxTV0EKS%2BfxRZfrMDg0fytq1eSDmkMZ9E%3D&reserved=0).
I know nothing about UWB, so I have no idea if the user interface
you propose here makes sense. My guess is that there is a good chance
that there are other implementations of UWB that would not work
with this specific driver interface, so you probably need a
slightly higher-level abstraction.

We had an older subsystem that was called UWB and that got removed
a while ago:

https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgit.kernel.org%2Fpub%2Fscm%2Flinux%2Fkernel%2Fgit%2Ftorvalds%2Flinux.git%2Fcommit%2Fdrivers%2Fstaging%2Fuwb%3Fid%3Dcaa6772db4c1deb5d9add48e95d6eab50699ee5e&data=05%7C01%7Cmanjunatha.venkatesh%40nxp.com%7C46c5718c03ee429cf57208dad2a3cad7%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C638053898170779252%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&sdata=XXYgofE9LlBCPGW1aKxKUOBEIGF0aQv%2Bh6x6iNATkLQ%3D&reserved=0

Is that the same UWB or something completely different?
Basically, it is SPI device driver which supports UCI(Ultra-wide band
Command Interface) packet structure. It is not same as in mentioned link.
Why isn't this just a normal SPI driver and you do the "UCI" commands
from userspace through the device node there?

I know I asked this before, but I can't remember the answer, sorry, so
please include that in the changelog information when you resubmit.

thanks,

greg k-h
The IO Handshake needed with SR1XX Family of SOCs cannot use the RAW SPI
Module's APIs and hence custom APIs are added for communication with the
UWBS,
I do not understand, what "IO handshake"? What is missing from the
userspace spi api that is needed here?

With this will get required throughput for UWBS use cases to avoid multiple
round trip between user and kernel mode.
Based on the speed of the SPI bus, this should not be an issue at all.
If it is, please provide us real performance numbers showing the
problem, as there are ways of speeding that up.

Not only throughput and also this driver customized ioctls to be controlled

from the user space for different scenarios.

Current driver have UCI (UWB Command Interface) specific header parsing logic.

There is a specific GPIOs hand shake mechanism required between Host Driver and UWBS

at driver level which is tightly coupled with our UWBS chip.

Basically UWBS expecting acknowledgement from Host driver after first interrupt request

triggered then Host driver acknowledge to UWBS through dedicated GPIOs.

After this one more interrupt request will be triggered from UWBS for read operation.

thanks,

greg k-h