Re: [PATCH 5/5] PCI: brcmstb: disable L0s component of ASPM by default

From: Jim Quinlan
Date: Thu Apr 30 2020 - 17:17:30 EST


On Thu, Apr 30, 2020 at 4:40 PM Bjorn Helgaas <helgaas@xxxxxxxxxx> wrote:
>
> On Thu, Apr 30, 2020 at 02:55:22PM -0400, Jim Quinlan wrote:
> > From: Jim Quinlan <jquinlan@xxxxxxxxxxxx>
> >
> > Some informal internal experiments has shown that the BrcmSTB ASPM L0s
> > savings may introduce an undesirable noise signal on some customers'
> > boards. In addition, L0s was found lacking in realized power savings,
> > especially relative to the L1 ASPM component. This is BrcmSTB's
> > experience and may not hold for others. At any rate, we disable L0s
> > savings by default unless the DT node has the 'brcm,aspm-en-l0s'
> > property.
>
> I assume this works by writing the PCIe Link Capabilities register,
> which is read-only via the config space path used by the generic ASPM
> code, so that code thinks the device doesn't support L0s at all.
Correct.
>
> Documentation/devicetree/bindings/pci/rockchip-pcie-host.txt includes
> an "aspm-no-l0s" property. It'd be nice if this could use the same
> property.
I'd like to use the existing "aspm-no-l0s" but we'd really like to
have it disabled by default. I'll probably switch but let me dwell on
it a little.
Thanks, Jim
>
> > Signed-off-by: Jim Quinlan <jquinlan@xxxxxxxxxxxx>
> > ---
> > drivers/pci/controller/pcie-brcmstb.c | 14 +++++++++++++-
> > 1 file changed, 13 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c
> > index 2bc913c0262c..bc1d514b19e4 100644
> > --- a/drivers/pci/controller/pcie-brcmstb.c
> > +++ b/drivers/pci/controller/pcie-brcmstb.c
> > @@ -44,6 +44,9 @@
> > #define PCIE_RC_CFG_PRIV1_ID_VAL3 0x043c
> > #define PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK 0xffffff
> >
> > +#define PCIE_RC_CFG_PRIV1_LINK_CAPABILITY 0x04dc
> > +#define PCIE_RC_CFG_PRIV1_LINK_CAPABILITY_ASPM_SUPPORT_MASK 0xc00
> > +
> > #define PCIE_RC_DL_MDIO_ADDR 0x1100
> > #define PCIE_RC_DL_MDIO_WR_DATA 0x1104
> > #define PCIE_RC_DL_MDIO_RD_DATA 0x1108
> > @@ -696,7 +699,7 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie)
> > int num_out_wins = 0;
> > u16 nlw, cls, lnksta;
> > int i, ret;
> > - u32 tmp;
> > + u32 tmp, aspm_support;
> >
> > /* Reset the bridge */
> > brcm_pcie_bridge_sw_init_set(pcie, 1);
> > @@ -806,6 +809,15 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie)
> > num_out_wins++;
> > }
> >
> > + /* Only support ASPM L1 unless L0s is explicitly desired */
> > + aspm_support = PCIE_LINK_STATE_L1;
> > + if (of_property_read_bool(pcie->np, "brcm,aspm-en-l0s"))
> > + aspm_support |= PCIE_LINK_STATE_L0S;
> > + tmp = readl(base + PCIE_RC_CFG_PRIV1_LINK_CAPABILITY);
> > + u32p_replace_bits(&tmp, aspm_support,
> > + PCIE_RC_CFG_PRIV1_LINK_CAPABILITY_ASPM_SUPPORT_MASK);
> > + writel(tmp, base + PCIE_RC_CFG_PRIV1_LINK_CAPABILITY);
> > +
> > /*
> > * For config space accesses on the RC, show the right class for
> > * a PCIe-PCIe bridge (the default setting is to be EP mode).
> > --
> > 2.17.1
> >