[PATCH 3/5] PCI: brcmstb: enable CRS

From: Jim Quinlan
Date: Thu Apr 30 2020 - 15:01:02 EST


From: Jim Quinlan <jquinlan@xxxxxxxxxxxx>

Configuration Retry Request Status is off by default on this
PCIe controller. Turn it on.

Signed-off-by: Jim Quinlan <jquinlan@xxxxxxxxxxxx>
---
drivers/pci/controller/pcie-brcmstb.c | 9 +++++++++
1 file changed, 9 insertions(+)

diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c
index 5b0dec5971b8..2bc913c0262c 100644
--- a/drivers/pci/controller/pcie-brcmstb.c
+++ b/drivers/pci/controller/pcie-brcmstb.c
@@ -34,6 +34,9 @@
#define BRCM_PCIE_CAP_REGS 0x00ac

/* Broadcom STB PCIe Register Offsets */
+#define PCIE_RC_CFG_PCIE_ROOT_CAP_CONTROL 0x00c8
+#define PCIE_RC_CFG_PCIE_ROOT_CAP_CONTROL_RC_CRS_EN_MASK 0x10
+
#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1 0x0188
#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK 0xc
#define PCIE_RC_CFG_VENDOR_SPCIFIC_REG1_LITTLE_ENDIAN 0x0
@@ -827,6 +830,12 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie)
pci_speed_string(pcie_link_speed[cls]), nlw,
ssc_good ? "(SSC)" : "(!SSC)");

+ /* Enable configuration request retry (CRS) */
+ tmp = readl(base + PCIE_RC_CFG_PCIE_ROOT_CAP_CONTROL);
+ u32p_replace_bits(&tmp, 1,
+ PCIE_RC_CFG_PCIE_ROOT_CAP_CONTROL_RC_CRS_EN_MASK);
+ writel(tmp, base + PCIE_RC_CFG_PCIE_ROOT_CAP_CONTROL);
+
/* PCIe->SCB endian mode for BAR */
tmp = readl(base + PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1);
u32p_replace_bits(&tmp, PCIE_RC_CFG_VENDOR_SPCIFIC_REG1_LITTLE_ENDIAN,
--
2.17.1