Re: [PATCH 8/8] x86, cleanups: Simplify sync_core() in the case ofno CPUID

[Borislav Petkov]

On Thu, Nov 29, 2012 at 01:20:00PM -0800, H. Peter Anvin wrote:
> On 11/29/2012 01:18 PM, Borislav Petkov wrote:
> > On Thu, Nov 29, 2012 at 01:06:20PM -0800, H. Peter Anvin wrote:
> >> It doesn't matter in that context, as the surrounding MSR references
> >> have barriers, but what I'm refering to is the "memory" barrier.
> > 
> > Ok, but the only difference between the two versions is this line:
> > 
> >         movl    %esi, %ecx      # tmp144, ecx
> > 
> > coming from the cpuid_eax() function. So the memory barrier is the same
> > and in the right place in both cases.
> > 
> 
> In the case of that one call site, yes, because the MSR references
> include the barrier.  Other sites, current or future, may not have the
> same property.

Sorry, but I think we're misunderstanding each other in some way, so let
me restart. Here's the version I'm suggesting:

static inline void sync_core(void)
{
	int tmp;

#ifdef CONFIG_M486
	/*
	 * Do a CPUID if available, otherwise do a jump.  The jump
	 * can conveniently enough be the jump around CPUID.
	 */
	asm volatile("cmpl %2,%1\n\t"
		     "jl 1f\n\t"
		     "cpuid\n"
		     "1:"
		     : "=a" (tmp)
		     : "rm" (boot_cpu_data.cpuid_level), "ri" (0), "0" (1)
		     : "ebx", "ecx", "edx", "memory");
#else
	/*
	 * CPUID is a barrier to speculative execution. Prefetched instructions
	 * are automatically invalidated when modified.
	 */
	tmp = cpuid_eax(1);

	/*
	asm volatile("cpuid" : "=a" (tmp) : "0" (1)
		     : "ebx", "ecx", "edx", "memory");
	*/
#endif
}

with the last asm volatile("cpuid"...) commented out. The only
non-trivial difference between the two is the zeroing out of %ecx when
looking at the resulting asm.

Now, cpuid_eax is actually native_cpuid() which has the memory barrier
character by having an "asm volatile" in there too and it too clobbers
memory.

Are you saying that there's a semantic difference between the naked
"asm volatile" and the compiler inlining a couple of inline functions
resulting in the same "asm volatile" memory barrier for it?

Hmm, strange.

-- 
Regards/Gruss,
    Boris.
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