Re: Virtual alias cache coherency results (was: x86, ARM, PARISC, PPC, MIPS and Sparc folks please run this)

[Jamie Lokier]

Russell King wrote:
> > Does your fix, which makes pages uncacheable andq disables write
> > combining (correct?) only fix your test results which intermittently
> > reported write buffer problems, or does it fix _all_ the ARM test
> > results I received, including those which don't report write buffer
> > problems?
> 
> It's relatively simple, and I'm not sure why its causing such
> misunderstanding.  Let me try one more time:
> 
> ARM caches are VIVT.  VIVT caches have inherent aliasing issues.  The
> kernel works around these issues by marking memory uncacheable where
> appropriate, and will continue to do so for VIVT cached ARM CPUs.

That I understand fully.

My question arises because I have 3 SA-110 results which report "cache
not coherent".  They do not report "store buffer not coherent".  All 3
are Rebel Netwinders, of different bogomips ratings.

The point is: those results _don't_ indicate write buffer problems.

It means that your VIVT explanation and workaround does not explain
those results, so I cannot have confidence that your workaround fixes
those particular ARM devices.

Now, if you can assure me that those results are _definitely_ due to
using very old kernels which don't even mark pages uncacheable, and
with newer kernels those Netwinders would exhibit coherent virtual
aliases, that's great.

Then I'll say that ARM Linux offers coherent virtual aliases on all
known ARM systems, provided they're running a sufficiently new kernel.

Otherwise, I can't say that.

-- Jamie
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