Re: Efficient IPC mechanism on Linux

[Jamie Lokier]

Arjan van de Ven wrote:
> > I have just done a measurement on a 366MHz PII Celeron
> 
> This test is sort of the worst case against my argument:
> 1) It's a cpu with low memory bandwidth
> 2) It's a 1 CPU system
> 3) It's a pII not pIV; the pII is way more efficient cycle wise
>    for pagetable operations

I thought that later generation CPUs were supposed to have lower
memory bandwidth relative to the CPU core, so CPU operations are
better than copying.  Hence all the fancy special memory instructions,
to work around that.

Not that it matters.  I think the 366 Celeron is typical of a lot of
computers being used today.  I still use it every day, after all.

-- Jaie

-
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@xxxxxxxxxxxxxxx
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/