> I don't think that non-cache-coherency wrt DMA necessarily means that
> that is true, though. If you flush all CPU caches to memory before
> starting the DMA, and you invalidate the DMA'd memory range _after_
> the DMA finished, a "prefetch" on such an architecture is not a
> problem at all.
OK -- assuming you actually do flush before the DMA and invalidate
afterwards, that works. That's what I was missing; thanks :)
That's for a prefetch operation which doesn't mark the cache line
dirty/owned. If you have random addresses used with 'write prefetch'
operations, that's still going to be a problem.
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This archive was generated by hypermail 2b29 : Wed Aug 07 2002 - 22:00:22 EST