On Sat, 3 Aug 2002, David Woodhouse wrote:
> Not that I'm necessarily disagreeing with you -- but can you confirm that
> you are including all architectures with non-cache-coherent DMA in the
> 'broken hardware' category below, or point out what I'm missing?
Rule: if prefetch to random addresses is a problem, then that's broken
I don't think that non-cache-coherency wrt DMA necessarily means that that
is true, though. If you flush all CPU caches to memory before starting the
DMA, and you invalidate the DMA'd memory range _after_ the DMA finished, a
"prefetch" on such an architecture is not a problem at all.
Sure, the data vould have been (for a while - between the potential
prefetch and the "DMA write finish invalidate") in the CPU caches in a
non-coherent state, but since the kernel reading anything from that region
would have been a bug in the first place, that should not matter.
Note that such architectures have issues with speculative reads etc too,
which can have all the same issues as prefetch. Of course, only slow and
stupid architectures tend to have non-coherent caches in the first place,
so "speculation" simply isn' tmuch of an issue.
(That's not to say that I think that non-coherent DMA is broken _anyway_,
but I don't think it should be a problem for prefetch itself)
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This archive was generated by hypermail 2b29 : Wed Aug 07 2002 - 22:00:22 EST