Re: [PATCH] 2.4.17/2.5.1 apic.c LVTERR fixes

From: Maciej W. Rozycki (
Date: Fri Jan 04 2002 - 07:12:44 EST

On Thu, 3 Jan 2002, Mikael Pettersson wrote:

> > Also note that's really an APIC and not a kernel bug -- writing a
> >previously read value to a register is defined as valid by Intel.
> Can you quote chapter and verse on that last statement?
> (Preferably from IA32 Vol3.) Writes to APIC registers obviously
> _do_ cause side-effects in some cases...

 Obviously I confused defined bits with reserved ones, sorry. Still the
APIC looks insane for me -- it should really signal an error only once an
interrupt is received, like it does for interrupts from remote sources.

> Pentium erratum 3AP can be ignored, since the whole purpose of the
> two ESR accesses is to clear ESR. Unfortunately, Pentium erratum 11AP
> does apply, since there are back-to-back APIC writes (first to LVTERR,
> then to ESR).

 I checked 3AP and you are right, since we don't need the ESR's value.

> + if (maxlvt > 3) /* Due to Pentium errata 3AP and 11AP. */
> + apic_write(APIC_ESR, 0);

 Use apic_write_around() instead as the 11AP workaround -- it was
introduced specifically for this purpose. Using anything else doesn't
guarantee no back-to-back APIC writes due to interrupts (specifically
writes to the EOI register).

+  Maciej W. Rozycki, Technical University of Gdansk, Poland   +
+        e-mail:, PGP key available        +

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