On Thu, 3 Jan 2002 15:57:34 +0100 (MET), Maciej W. Rozycki wrote:
>> @@ -84,6 +88,8 @@
>> apic_write_around(APIC_LVTERR, APIC_LVT_MASKED);
>> if (maxlvt >= 4)
>> apic_write_around(APIC_LVTPC, APIC_LVT_MASKED);
>> + apic_write(APIC_ESR, 0);
>> + v = apic_read(APIC_ESR);
>> }
>
> You mustn't access the ESR unconditionally -- it doesn't exist in the
>i82489DX. Also check the Pentium erratum 3AP for possible issues (I can't
>recall if writing is safe -- possibly only the contents are lost).
>
> Also note that's really an APIC and not a kernel bug -- writing a
>previously read value to a register is defined as valid by Intel.
Can you quote chapter and verse on that last statement?
(Preferably from IA32 Vol3.) Writes to APIC registers obviously
_do_ cause side-effects in some cases...
Pentium erratum 3AP can be ignored, since the whole purpose of the
two ESR accesses is to clear ESR. Unfortunately, Pentium erratum 11AP
does apply, since there are back-to-back APIC writes (first to LVTERR,
then to ESR).
The patch below fixes the 11AP and 82489DX issues. It has the usual test
before the write to ESR, which avoids both erratum 11AP (should the code
be moved around) and 3AP (redundantly, to avoid confusion).
(Linus, please apply.)
/Mikael
--- linux-2.5.2-pre6/arch/i386/kernel/apic.c.~1~ Thu Jan 3 19:08:00 2002
+++ linux-2.5.2-pre6/arch/i386/kernel/apic.c Thu Jan 3 19:58:26 2002
@@ -88,8 +88,12 @@
apic_write_around(APIC_LVTERR, APIC_LVT_MASKED);
if (maxlvt >= 4)
apic_write_around(APIC_LVTPC, APIC_LVT_MASKED);
- apic_write(APIC_ESR, 0);
- v = apic_read(APIC_ESR);
+ v = GET_APIC_VERSION(apic_read(APIC_LVR));
+ if (APIC_INTEGRATED(v)) { /* !82489DX */
+ if (maxlvt > 3) /* Due to Pentium errata 3AP and 11AP. */
+ apic_write(APIC_ESR, 0);
+ apic_read(APIC_ESR);
+ }
}
void __init connect_bsp_APIC(void)
-
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This archive was generated by hypermail 2b29 : Mon Jan 07 2002 - 21:00:22 EST