Re: IRQ affinity vs. MTRRs, was Re: 36 bit MTRRs, Re: test10-pre1 problems on 4-way SuperServer8050

From: Boszormenyi Zoltan (
Date: Thu Oct 12 2000 - 08:47:26 EST

On 12 Oct 2000, David Wragg wrote:

> Boszormenyi Zoltan <> writes:
> > I came up with an idea. The MTRRs are per-cpu things.
> > Ingo Molnar's IRQ affinity code helps binding certain
> > IRQ sources to certain CPUs.
> They are implemented as per-cpu things but the Intel manuals say that
> all cpus should have the same MTRR settings. They also give
> pseudo-code for how to update them on an SMP system, which mtrr.c
> follows.
> If the BIOS has set them up differently at boot time, mtrr.c will
> complain and copy the MTRR settings of CPU0 to the others.

Yes, I read the Intel manuals and I know how the mtrr driver works.

The idea is that when it is sure that _only one_ (or some) CPU will access
a PCI card's mmio area then only that CPU's (those CPUs') MTRRs needs to
contain an entry for that area.

Although there are (must be) common MTRR entries for the main memory
and the commonly accessed mmio register areas.

The idea came because fiddling with MTRRs quickly revaled that
only 8 variable ones exist.

Zoltan Boszormenyi

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