Re: IRQ affinity vs. MTRRs, was Re: 36 bit MTRRs, Re: test10-pre1 problems on 4-way SuperServer8050

From: David Wragg (
Date: Thu Oct 12 2000 - 09:31:45 EST

Boszormenyi Zoltan <> writes:
> The idea is that when it is sure that _only one_ (or some) CPU will access
> a PCI card's mmio area then only that CPU's (those CPUs') MTRRs needs to
> contain an entry for that area.
> Although there are (must be) common MTRR entries for the main memory
> and the commonly accessed mmio register areas.
> The idea came because fiddling with MTRRs quickly revaled that
> only 8 variable ones exist.

I see. I think there is a more straightforward solution: PAT does the
same thing as MTRRs, but has no such "number of ranges" limitation ---
it lets you set the memory type on a page-by-page basis. If the
number of MTRRs becomes a problem (anyone know how many the P4 has?),
then the real solution is to implement PAT support.

IIRC, only the PPro, the first PII model (Klamath?), and the first
Celeron model have MTRR but not PAT (Athlon has PAT, but /proc/cpuinfo
misreports it as "fcmov", at least in 2.2.14; Xeons always had PAT).

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