Date: Tue, 20 Jun 2000 20:29:24 -0400 (EDT)
From: James Simmons <jsimmons@acsu.buffalo.edu>
I know SGI hardware for example has some of it graphics register
regions mapped to non caching memory and some to caching memory
regions.
This is old hat, it can be done with the Sun cards as well.
Essentially, the card has a basic rule that "writing to this register
must be last and it snapshots all attributes and draws the
line/rectangle/whatever" so you map the accelerator mappings twice,
once with store-merging/caching/reordering allowed, one without, and
you go:
chip_cacheable->color = red;
chip_cacheable->drawop = rectangle;
chip_cacheable->rop = GXcopy;
chip_cacheable->y = y_coord;
chip_cacheable->x = x_coord;
chip_cacheable->h = h_pixels;
chip_uncached->w = w_pixels;
And the cpu can merge all the stores up to the final uncached one
however it wishes etc. All the graphics card cares about is that
it sees the "w" coordinate write last, and it all works out.
They put certain register groups together in contiguous locations
so that store buffer merging into large writes on the bus happen
often.
Later,
David S. Miller
davem@redhat.com
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