Hi!
Some more info found, posting it hoping it is usefull for debugging:
[root@iq ide]# cat piix
Intel PIIX4 Ultra 33 Chipset.
--------------- Primary Channel ---------------- Secondary Channel
-------------
enabled enabled
--------------- drive0 --------- drive1 -------- drive0 ---------- drive1
------
DMA enabled: yes yes yes no
UDMA enabled: yes no yes no
UDMA enabled: 2 X 2 X
DMA
PIO
[root@iq ide]# cat cmd64x
CMD648 Chipset.
--------------- Primary Channel ---------------- Secondary Channel
-------------
enabled enabled
--------------- drive0 --------- drive1 -------- drive0 ---------- drive1
------
DMA enabled: no no no no
UDMA enabled: no no no no
UDMA enabled: 4 4 4 4
DMA enabled: 2 2 2 2
PIO
ARTTIM0 = 0x40, HI = 0x04, LOW = 0x00
DRWTIM0 = 0x3f, HI = 0x03, LOW = 0x0f
ARTTIM1 = 0x40, HI = 0x04, LOW = 0x00
DRWTIM1 = 0x3f, HI = 0x03, LOW = 0x0f
ARTTIM23 = 0x5c, HI = 0x05, LOW = 0x0c
DRWTIM2 = 0x3f, HI = 0x03, LOW = 0x0f
DRWTIM3 = 0x3f, HI = 0x03, LOW = 0x0f
UDIDETCR0 = 0xf0, HI = 0x0f, LOW = 0x00
UDIDETCR1 = 0xf0, HI = 0x0f, LOW = 0x00
[root@iq ide]#
-- SaPE
Peter, Sasi <sape@sch.hu>
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