On Wed, 1 Mar 2000, Linus Torvalds wrote:
>On Wed, 1 Mar 2000, Andrea Arcangeli wrote:
>>
>> Nothing goes wrong. What happens without the IRQ_LEVEL bit is this:
>>
>> CPU0 CPU1
>> ------------------ --------------------
>> do_IRQ(27, ...)
>> do_IRQ(27, ...)
>
>Ok, horrible interrupt distribution hardware. Fair enough.
Agreed ;). OTOH there's a minor pros with such SMP irq design that we are
forced to use: we kill irq latency best. IO-APIC AFIK chooses the CPU that
is handling the lower bus load at irq time, but it doesn't choose the CPU
that has irq enabled AFIK.
>From 24319201.pdf 7.4.10:
"From all processors listed in the destination, the processor
selected is the one whose current arbitration priority is the
lowest."
Andrea
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