On Mon, 14 Feb 2000, Richard B. Johnson wrote:
> Of course this response has no basis in fact. The problem was traced
> to the printer-port enable being a tri-state enable. The TTL (actually
> PMOS) version of the controller didn't care that its input was left
> floating. However, when substituting the CMOS version, we were left
> with a floating input because there was no pull-up resistor on this
> input. The fix was a resistor.
Go read the 8259A datasheet (it's Intel order number 231468). It's about
the original NMOS version so your CMOS reference is irrelevant. Search
the doc for the default vector.
Now tell me what the circuit does when it receives two INTA cycles but no
IRR bit is set because no new interrupts arrived and all previous were
acknowledged? Don't you know? Go fetch an MP-compliant SMP system and
route an ExtINTA IRQ via both a local unit and via an I/O unit. Observe
what an 8259A does when it receives the second pair of INTA cycles. Or
what it does when it receives a pair of INTA cycles while all IRQ sources
are masked out. Of course this description is simplified, but since you
are an experienced interrupt programmer you will easily figure out missing
implementation details.
Finally, please tell me how do you imagine performing "IRQ latching" for
level-triggered interrupts. I've no idea how it could be done (and what
for). Of course no real latching is done by an 8259A for either trigger
type interrupts -- if an IRQ is deasserted, it's forgotten -- the
respective IRR bit gets cleared.
Please learn facts and do not spread myths -- someone less experienced
might actually believe you...
-- + Maciej W. Rozycki, Technical University of Gdansk, Poland + +--------------------------------------------------------------+ + e-mail: macro@ds2.pg.gda.pl, PGP key available +- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.rutgers.edu Please read the FAQ at http://www.tux.org/lkml/
This archive was generated by hypermail 2b29 : Tue Feb 15 2000 - 21:00:29 EST