On Tue, 15 Feb 2000, Richard B. Johnson wrote:
On Tue, 15 Feb 2000, Maciej W. Rozycki wrote:
> On Mon, 14 Feb 2000, Richard B. Johnson wrote:
>
> > Of course this response has no basis in fact. The problem was traced
> > to the printer-port enable being a tri-state enable. The TTL (actually
> > PMOS) version of the controller didn't care that its input was left
> > floating. However, when substituting the CMOS version, we were left
> > with a floating input because there was no pull-up resistor on this
> > input. The fix was a resistor.
>
> > Go read the 8259A datasheet (it's Intel order number 231468). It's about
> > the original NMOS version so your CMOS reference is irrelevant. Search
> > the doc for the default vector.
> >
Once programmed, there is no 'default vector'. The upper 5 bits of the
vector are set in ICW2. If there are no interrupt requests pending, there
are no vectors. Period.
> Now tell me what the circuit does when it receives two INTA cycles but no
> IRR bit is set because no new interrupts arrived and all previous were
> acknowledged? Don't you know? Go fetch an MP-compliant SMP system and
> route an ExtINTA IRQ via both a local unit and via an I/O unit. Observe
> what an 8259A does when it receives the second pair of INTA cycles. Or
> what it does when it receives a pair of INTA cycles while all IRQ sources
> are masked out. Of course this description is simplified, but since you
> are an experienced interrupt programmer you will easily figure out missing
> implementation details.
INTA Cycles come from the CPUs, not from the controller. If the
CPUs were to generate such an ACK, without a coresponding request,
the CPUs are broken. The controllers were of course not designed
to control two or more CPUs. For this reason, the board vendors do
not feed the INT output to all the CPUs in parallel, they select
each one in turn through a ripple-counter. This has the unfortunate
consequence of missing interrupts until all the CPUs have been
initialized. It also means that a dual-CPU SMP machine that was not
properly hardware-reset (i.e. warm-boot), may miss every-other interrupt
upon startup.
You can simulate the response to an INTA (from the CPU) by setting
the D2 bit in OCW3. It sets the highest requesting level in the
in-service register and generates the vector that would be put
on the address-lines for the vectored interrupt. On the next read
the data returned will have the value D0-D2 of the interrupt request.
You don't have to send a physical INTA to the device(s), possibly
killing your system. If the IR bits are all masked off, you will
note that no such vector is generated. This shows that there is
no "default vector".
All this information is available in a book written by Lewis C.
Eggebrecht, "Interfacing to the IBM Personal Computer", Howard W.
Sams, Inc. ISBN 0-672-22027-X. He designed the first IBM PCs and
the System 23. This is an "Old book, circa 1983" , but so is
the 8259A.
Reference to these "original works" should help reduce the amount
of folklore associated with the devices used in the PC machines.
>
> Finally, please tell me how do you imagine performing "IRQ latching"
> for
> level-triggered interrupts. I've no idea how it could be done (and what
> for). Of course no real latching is done by an 8259A for either trigger
> type interrupts -- if an IRQ is deasserted, it's forgotten -- the
> respective IRR bit gets cleared.
>
ALL IRQ inputs to the 8259A are latched. This is how it is able to
remember the inputs so the programmed priority can work.
Once an interrupt-request line remains true for the required setup
time, that input bit is latched. The physical device can 'buzz', deassert
its request or do whatever it wants. The fact that an interrupt request
occurred is sufficient for the controller to 'remember' it for all time.
It forgets it only when an EOI code is sent to the controller.
There are two, 0x20 is non-specific and 0x60|int_no is specific.
At this time, if the LTIM bit in the initialization register was not
set, the input latch is reset.
That's how it works.
The original 8259 was not designed for level-triggering, in fact
it was designed for use with 8085. It has a bit in ICW4 to select
the 8085 or the 8088 mode. The 'A' version and subsequent CMOS versions
provided a LTIM bit in the initialization register, ICW1 (bit 3). The
function of this bit is to prevent resetting the input latch when an EOI
(specific or non-specific) if sent to the device, IF the interrupt request
line is still true. This has the effect of allowing a level to be
detected. With this, multiple interrupt requests may be ORed into the same
IRQ line.
> Please learn facts and do not spread myths -- someone less experienced
> might actually believe you...
You, sir, are one spreading myths.
Cheers,
Dick Johnson
Penguin : Linux version 2.3.41 on an i686 machine (800.63 BogoMips).
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