> In a SMP box all CPU's have equal access to all memory. This does cause
> the exact problems that you describe. One solution to this is to give each
> CPU it's own memory, the problem then is that some parts of memory are
> easier to get at then others, depending on which CPU you are accessing
> them from. thus Non Uniform Memory Access machines (NUMA).
Another solution is to avoid the per-cpu caches. Yes - one big cache
for all processors. I believe this is hard to achieve on a circuit
board,
those low-latency caches need impressive signalling speed incompatible
with ten-centimeter distances. But it may be a good solution
for a dual/quad-on-a-chip cpu.
Helge Hafting
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