>Speculative reads are invalidated. This _only_ means that
>cpu1: store A; store B
>cpu2: read B, read A.
>if cpu2 read the new value of B, then it's always true that it gets the
>new value of A. (On my P/II 350, I'm not sure if this is officially
>documented)
I guess in the above case there's no problem because the reads are not
reordered. I guess a read become speculative only if there's a write
before the read.
>This means that the following could happen:
>
>cpu1 memory cpu2
> A=0
> A=1
XXX
>* into buffer
>* A=0
>* * cpu2 is a snob
>* * with a short buffer ;)
>* * my test program
>* *uses a rmb()
>* * to trigger that.
>* A=0 <--------
>*
>* cpu1 is lazy
>*
>*
>------> A=1
YYY
>
>As you see, although cpu2 has executed it's instruction after
>cpu1, the value from cpu1 'wins'.
That's not a problem. You have no garantee that the instruction will
happen at line XXX. So if it happens at XXX and you see it at YYY, you can
just assume the CPU executed the instruction at line YYY and you can as
well ignore the write buffer.
But if a read happens between XXX and YYY, then - to preserve processor
ordering - the hardware should invalidate such a speculative read if
another CPU changed the value that we read in speculative mode before YYY.
It seems to me the speculative read is not invalidated.
The point is that a read should be considered speculative (waiting to be
invalidated) until the write is _visible_ to all the other CPUs.
Andrea
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