No, we don't want to make ioremapped memory uncacheable.
On x86 where x < 6, external logic makes sure that non-memory accesses are
uncached even if the page tables say otherwise (the KEN bit, I do
believe). There are known cases where the motherboard is broken, but they
are very few and worked around already.
On x86 where x >=6, the MTRR's do the same job. That's why the MTRR's were
introduced: because the P6 core can re-order accesses, you can no longer
afford to wait until the access hits the bus to know whether it is RAM or
not, so you have to introduce a in-core data structure to maintain that
knowledge.
So note that we do NOT want to make all ioremapped accesses uncacheable,
because then we could no longer do clever tricks with MTRR's.
And we know that we want to do MTRR stuff, at least eventually.
Linus
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