Re: Are SMP spinlocks safe in WB cached mem ?

Robert Redelmeier (redelm@ev1.net)
Fri, 26 Nov 1999 09:32:50 -0800

Erich Boleyn wrote in part:
>
> Robert Redelmeier <redelm@ev1.net> wrote:
>
> ...
> > > First of all, for the LOCK to only go as far as the cache, then
> > > the line must be in a either of the M or E states. If it is in
> > > an S state, it must get into one of the M or E states first.
> >
> > Agreed as well per 9-3. But if you write to an S line, it becomes E.
>
> Sure, but the point is that, before the write or LOCK can take place,
> it has to do a Read-For-Ownership to the bus first, which, if successful,
> puts it into the new state. It doesn't just assume it can willy-nilly
> change the line into that state. That would be bad.

Now this is news. I wasn't aware there was a separate Read-For-Ownership
mode or signal. Of course, any P6 write that misses the cache causes a
cache line fill, but I wasn't aware that this was different from a normal
read. That would logically set "Invalid" on the other CPU.

This chitchat is nice, but a Linus says: "Show me the code" . And I've
been trying to break WB spinlocks by modifying Ingo's test code. No such
luck. I can have as many threads as I like pounding away on spinlocks
for 15-minutes to an hour without breakage. Yet slip a tight coupled
spin_unlock()/spin_lock() pair in, and it breaks immediately as it's
supposed to. So I have to admit WT spinlocks are safe, or I am stupid.
Or both :)

-- Robert

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