>And THAT is the assymetry: intel can and will re-order
>
> write A
> read B
I guess that almost all pipelined processors will reorder this (that's
not a speculative execution issue), because reads are performed early
in the pipeline and writes at the end. Suppose we have 5 stages
(fetch-decode-read-exec-write), then the above two instructions will
first read B and then write A.
T0 T1 T2 T3 T4 T5
write A fetch decode read exec write
read B fetch decode read exec write
The read happens in T3 and the write in T4. When doing:
write A
read A
the CPU can detect this and internally forward A from stage 4 directly
to stage 3. But this doesn't work with SMP since one CPU cannot look
into the pipeline of the other CPU.
Peter
--
_ x ___ p.steiner@t-online.de (Peter Steiner)
/ \_/_\_ /,--' Linux User #55148 (http://counter.li.org/)
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