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> for (;;) { for (;;) {
> i++; a = i;
> j++; b = j;
> } if (a < b)
> BUG()
> }
in fact with the attached testcode causality seems to break _easily_ on
Xeon CPUs:
moon:~> ./causal 2
<30> 9 11
<thread1> BROKE causality! Weakly ordered memory?
the code starts two threads which do the above test. Ie. we can _easily_
see stores on other CPUs in the wrong order.
So you and Manfred are right :) This means that the barrier changes in
smp-2.3.30-A1 still hold, plus i believe all ioremapped area has to be
made uncacheable on x86.
the barrier changes in smp-2.3.30-A1 are done only based on the rule that
writes never pass reads upwards. (reads can still pass reads upwards, and
reads can still pass writes upwards)
Ingo
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