Re: Are SMP spinlocks safe in WB cached mem?
Mikulas Patocka (mikulas@artax.karlin.mff.cuni.cz)
Thu, 25 Nov 1999 19:16:58 +0100 (CET)
> Having an SMP box, and noting all the SMP crash reports I did some
> light reading :) of the IA32 System Programming Manual. I came
> up with a scenario for P6 SMP spinlock corruption/theft:
>
> CPU0 has and clears spinlock SL. The write is still in cache not mem
> CPU1 tries to read SL.
> CPU0 sees the read and helpfully signals HITM# and passes the line.
> CPU1 starts receiving the line and sets SL
> CPU0 "simultaneously" sets SL in it's cache line.
When CPU0 starts passing cache line to CPU1, it sets it to SHARED state,
which prevents any atomic writes to it. If not, it's bug in CPU.
Mikulas Patocka
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