> In physics, this issue is called "causality" rather than "order", and I
> don't think the issue has really been clarified.
>
> Basically, everybody agrees on ordering of writes. Intel keeps them in
> order.
>
> What I still find to be the weak point of all the arguments both ways is
> that I still have NOT seen any real proof that CPU#1 could not see the
> "future" write of "b". In short, without a synchronizing instruction I
> don't trust causality - even though I trust order.
IA32 processors don't violate causality in WB & UC because stores are
not externally visible until they are committed state.
When I was loosely describing what "Processor Ordering", there was a
good reason to say that it was the same as Strong Ordering but with
potentially *delayed* stores. If you allow stores to speculatively
go out to the rest of the system, you can get causality violation, and
that is one of the properties of Weak Ordering.
The speculation features of IA32 are essentially irrelevant for WB &
UC. The rest of the machine makes it look strictly in-order.
Processor Ordering vs. Strong Ordering mainly allows you to relax having
to constantly broadcast all memory changes to all processors instantly,
which in an SMP system with lots of processors greatly improves
performance. It still preserves most of the better properties of
Strong Ordering like causality.
-- Erich Boleyn PMD Architecture <esboleyn@ichips.intel.com>- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.rutgers.edu Please read the FAQ at http://www.tux.org/lkml/