Note that this is not a new problem.
The only way to synchronize PCI reliably is to do a PCI read from the
_same_ device you wrote to, simply because you don't know how many bridges
etc there are.
The mb/wmb/rmb stuff is still required for PCI simply because other
platforms can actually allow writes to pass each other and get re-ordered,
and if you use "__raw_[write][read]X()" you need some way of handling
that.
Although we should probably have a "io[rw]mb()" thing for that, actually.
Overloading the memory barrier with the (local device) IO ordering barrier
is bad, and not strictly correct anyway (we'll need to do "sfence" even on
ia32 when we start using unordered uncached areas.. )
Linus
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