> Unfortunately it then goes on to say "Intel does not guarantee that
> future processors will support this model"
yes, but it will definitely be told wether a model supports this or not.
It's a really noticeable performance and cache footprint win, and there is
no problem at all to reintroduce a (saner) write-barrier later on if a
more advanced model is added. On 550MHz PIII Xeons there is no problem so
far with this.
-- mingo
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