It can only improve latency after some idle time. If your CPU are
under 100% of load for a long time you'll have to spend the
memset(0) time anyway
This means it does not hamper performance during these cases
compared to not having the zero'd page cache.
Also the idle task will be less fast in rescheduling itself.
I don't think 200 or so cycles will even show up on the radar.
However, this mentioned cycle cost is arch dependant, and this is why
it should be an architecture level decision whether or not to do
something like this.
Oh yes, there are other options available btw. There are machines
where DMA controllers exist which can be put into a zero'ing or
loopback mode to do the zero'ing work. And thus have no "cpu cost"
except to write the address to the register on the controller.
In fact Ingo once had a fun hack where he would make the disk
controller DMA from a set of blocks on his disk containing zeros to
obtain this effect. :-)
Later,
David S. Miller
davem@redhat.com
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