Re: Wrong bogomips after plugging in AC power

Ralf Baechle (
Tue, 2 Nov 1999 10:39:21 +0100

On Fri, Oct 29, 1999 at 09:08:47AM -0700, Jeremy Fitzhardinge wrote:

> I suspect I'll see a similar problem on the PowerPC. The PPC has a way of
> throttling the rate instructions are delivered from the icache to the execution
> units, and thereby reducing CPU power consumption/temperature. This slows down
> the effective instruction execution speed, but all the clocks are unchanged. In
> other words, udelay will break, but timing based on the timebase or decrementer
> registers will be unaffected.

The R4000-style (not R4600-style) MIPS processor have a RP (Reduce Power)
bit in the the status register which when set will reduce the clock rate.
Of course the manuals don't define if this also affects the cycle counter
or not.

(Worse, the RP bit is documente in the manuals and the fineprint in some
erratas says this bit isn't implemented ...)


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