> Dick Johnson wrote:
>
> > align 2 ; Get off DWORD boundary
> > not [ebx] ; Invert memory byte
> > push eax ; Exercise the bus
> > pop eax
> > cmp eax, [ebx] ; See if it took
> > mov [ebx], ecx ; Put original back
>
> Does this work even with write back L1/L2 caches? I'm using a 2-pass
> algorithm to make sure the data really is written back and reread.
Yes. Note that I write only one longword, then force new data onto
the bus by pushing/popping. They I read back. The cache is not going
to be loaded/reloaded from a single longword access. The next access
is a whole page away. You have to worry about 'virtual' read/writes
into the cache only if you are doing sequential access.
Cheers,
Dick Johnson
Penguin : Linux version 2.3.13 on an i686 machine (400.59 BogoMips).
Warning : It's hard to remain at the trailing edge of technology.
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