Hi,
AMD processors newer than k5-100 stepping 0 have extended cpuid
function 0x80000005 to report cache size (and type). I've written a
small patch to allow not only Athlon to display info about the cache
sizes but k6,k6-2,k6-III too. The patch also fixes a cpu
capabilities misreport by the amd-k5.
patch attached
thanks
-- Catalin Muresan CODEC Electronic Products Internet Services Department 504054.79 403356.05--k+w/mQv8wyuph6w0 Content-Type: text/plain; charset=us-ascii Content-Disposition: attachment; filename=patch-k6
--- arch/i386/kernel/setup.c.orig Tue Oct 26 12:11:35 1999 +++ arch/i386/kernel/setup.c Tue Oct 26 15:19:34 1999 @@ -734,14 +734,22 @@ static int __init get_model_name(struct cpuinfo_x86 *c) { - unsigned int n, dummy, *v; + unsigned int n, dummy, *v, ecx, edx; /* Actually we must have cpuid or we could never have * figured out that this was AMD from the vendor info :-). */ cpuid(0x80000000, &n, &dummy, &dummy, &dummy); - if (n < 4) + if((boot_cpu_data.x86_model == 5) && + (boot_cpu_data.x86_mask == 0)) { + /* arly AMD K5 processors (SSA5) falsely used APIC bit to + * report PGE support. + */ + c->x86_capability &= ~X86_FEATURE_APIC; + c->x86_capability |= X86_FEATURE_PGE; + } + if (n < 0x80000004) return 0; cpuid(0x80000001, &dummy, &dummy, &dummy, &(c->x86_capability)); v = (unsigned int *) c->x86_model_id; @@ -757,6 +765,17 @@ (boot_cpu_data.x86_mask >= 8))) c->x86_capability |= X86_FEATURE_MTRR; + if (n >= 0x80000005){ + cpuid(0x80000005, &dummy, &dummy, &ecx, &edx); + printk("CPU: L1 I Cache: %dK L1 D Cache: %dK\n", + ecx>>24, edx>>24); + c->x86_cache_size=(ecx>>24)+(edx>>24); + } + if (n >= 0x80000006){ + cpuid(0x80000006, &dummy, &dummy, &ecx, &edx); + printk("CPU: L2 Cache: %dK\n", ecx>>16); + c->x86_cache_size = ecx>>16; + } return 1; } @@ -826,14 +845,6 @@ break; case 6: /* An Athlon. We can trust the BIOS probably */ { - - u32 ecx, edx, dummy; - cpuid(0x80000005, &dummy, &dummy, &ecx, &edx); - printk("L1 I Cache: %dK L1 D Cache: %dK\n", - ecx>>24, edx>>24); - cpuid(0x80000006, &dummy, &dummy, &ecx, &edx); - printk("L2 Cache: %dK\n", ecx>>16); - c->x86_cache_size = ecx>>16; break; }
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