Hi
these are patches for proper detection of Second level cache for today
released Intel Coppermine processor.
When CPUID is executed on a processor with 256K cache, the result in eax
is a bit different than the rest of the processors.
Bit 6 is shifted left so instead of getting 0x42 we get 0x82.
e.g. "100 0010" becomes "1000 0010"
NOTE: This is valid only for 256K cache processors 512K return as
expected 0x43
--------------BEA4D26A42A6D7DA020A5DA2
Content-Type: text/plain; charset=us-ascii;
name="coppermine.2.2.13"
Content-Transfer-Encoding: 7bit
Content-Disposition: inline;
filename="coppermine.2.2.13"
--- arch/i386/kernel/setup.c Tue Oct 19 17:14:00 1999
+++ arch/i386/kernel/setup.c Mon Oct 25 17:07:02 1999
@@ -17,6 +17,9 @@
*
* IDT Winchip tweaks, misc clean ups.
* Dave Jones <dave@powertweak.com>, August 1999
+ *
+ * Added proper L2 cache detection for Coppermine
+ * Dragan Stancevic <visitor@valinux.com>, October 1999
*/
/*
@@ -838,6 +841,7 @@
break;
case 0x42:
+ case 0x82: /*Detect 256-Kbyte cache on Coppermine*/
cache_size = 256;
break;
--------------BEA4D26A42A6D7DA020A5DA2
Content-Type: text/plain; charset=us-ascii;
name="coppermine.2.3.23"
Content-Transfer-Encoding: 7bit
Content-Disposition: inline;
filename="coppermine.2.3.23"
--- arch/i386/kernel/setup.c Fri Oct 22 10:30:27 1999
+++ arch/i386/kernel/setup.c Mon Oct 25 16:52:14 1999
@@ -29,6 +29,8 @@
* Cleaned up cache-detection code
* Dave Jones <dave@powertweak.com>, October 1999
*
+ * Added proper L2 cache detection for Coppermine
+ * Dragan Stancevic <visitor@valinux.com>, October 1999
*/
/*
@@ -1233,6 +1235,7 @@
break;
case 0x42:
+ case 0x82: /*Detect 256-Kbyte cache on Coppermine*/
c->x86_cache_size = 256;
break;
--------------BEA4D26A42A6D7DA020A5DA2--
-
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