Thats how modern PCI cards work. It isnt as horrying as it sounds. the
store buffer on PCI is ordered and reads don't occur until the store
buffer is emptied - so ordering is preserved.
If you look at something like I2O you will see that the whole setup is
geared to posting. You post requests to the card, it posts replies to your
memory. The only stall is getting a new message to fill.
On the memory side you take a cache miss from the DMA from the card but
on an AMD Athlon you can even prefetch that.
> Note that this is unconditional branch, and if the branch target address
> is computed sufficiently ahead of the branch instruction there will be
> no penalty.
There is the jump/return overhead. There is the stack management overhead
There is an extra cache line touched.
> > documentation on the IA64 to see what we might expect from the future,
> > branches are expensive.
>
> Have Intel released docs about some implementation of the architecture ?
All the basic userland stuff is released. Its very pa-risc.
Alan
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