> > configuring LINT0 as NMI as well, although i feel uneasy about this hack,
> > we do have legitimate cases of through-local-APIC interrupts - which would
> > thus become NMIs. It's also horribly dangerous because i have to ack the
> > 8259A IRQ0 interrupt from within the NMI handler - shudders. And it
>
> No, no, no. Although MPS does not explicitly forbide ceasing to connect
> of any IRQ lines to I/O APICs, in real life the only IRQs that may be
> unconnected are IRQ0 and IRQ13 due to legacy EISA chipsets. As we do not
... except for the fact that there _are_ motherboards which have no IRQ0
connected to the IOAPIC, and their mptable lies about this fact. This is
why we need mixed mode, or at least this is one of the reasons why we do
not (yet) want to kill LINT0 based interrupts, yet.
> care of EISA DMA chaining interrupts (do we?), we may set up IRQ0 as a
> "through-8259A" interrupt which is more reliable and it needs no acking at
> all. [...]
what exactly do you mean here? To set up LINT0 as ExtINT and to unmask
IRQ0 in the 8259A, and to mask the IOAPIC pin? Or to set up the according
IOAPIC routing entry as ExtINT? The later one is completely pointless - if
there is an IOAPIC pin for IRQ0 then we want that to be a LowPrio IRQ. If
we set it up through the local APIC's LINT0 pin, then we lose the ability
to route to multiple CPUs. (it makes no difference that the 8259A's INTR
output signal is driven to all CPUs, there is no mechanizm to distribute
this between CPUs, we'd get an interrupt on all CPUs at once, and had to
do some sort of software-selection - clearly complex and suboptimal.)
> > is yet another trick to be tried: we can also set up the local APIC's
> > performance counter LVT into NMI mode, and switch on the performance
> > counter that counts timer cycles ... then we'll get periodic NMIs. I'm
> > pretty much dedicated now to get the NMI oopser done without impacting
> > IRQ0 distribution.
>
> How would you perform this? The PC does not provide a configurable
> delivery mode -- it's always "Fixed". And even if it would it's
no, delivery mode can be configured for PCINT.
> completely unportable -- it does not exist on i486 and Pentium systems at
> all.
and? The NMI oopser doesnt work on UP boxes either.
-- mingo
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