Re: New resources - pls, explain :-(

Paul Mackerras (paulus@cs.anu.edu.au)
Fri, 13 Aug 1999 22:56:03 +1000


Jes Sorensen <Jes.Sorensen@cern.ch> wrote:

> Now that you bring this up here it might be a good idea to mention
> that we (you and I both included) have just been discussing this in a
> different forum and there is disagreement between the Alpha and PPC
> camps on this one.

I didn't think the PPC camp was actually united on this one. I got
the impression that it was me vs. the rest of the world. :-)

(I exaggerate. Alan Cox said that not reordering was a safer default
(which is essentially my position) and Dave Miller said to me in
private email something along the lines that any sane architecture has
a side-effect bit in the PTEs to prevent reordering of accesses to
certain pages.)

> My point is that the current implementation expects no protection
> against reordering and many current device drivers already deal with
> this correctly (I checked the aic7xxx this this morning and I noticed
> that it deals with this explicitly, even on the PPC).

Richard Henderson mentioned four drivers which he uses which deal with
this: ncr, aic7xxx, tulip, epic100. How many others would there be in
this category? It sounds to me like the vast majority of drivers
which use readl/writel would be assuming that they prevent reordering.

My position is that readl/writel should prevent reordering (of the
accesses generated by read*/write*), and that we should have variants,
maybe called readl_fast etc., for the cases where performance is
crucial and the driver writer is willing to put in explicit barriers
where necessary.

IMHO the time spent doing readl/writel is absolutely insignificant in
the vast majority of cases. If you have to feed a device so fast that
the time spent doing readl/writel is significant, then you should
either be using DMA (or for a framebuffer, a graphics engine) or you
should be feeding it from user level (as in the case of a 3D graphics
card).

Interestingly, the 4 drivers mentioned by Richard all do DMA (AFAIK).
Which leads me to wonder why the speed of readl/writel is so
significant that it is necessary to have the barriers explicit in the
driver instead of including them in readl/writel. Surely those
drivers can't be doing more than a couple of readl/writel per packet
or block?

Regards,
Paul.

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